CYW173SXC【PDF 1/5 页】IC CLK GEN TAPE DRV 4CH 16SOIC

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Sheet目录1992

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Tape Drive Frequency Timing Generator

W173

..........Document #: 38-07313 Rev. *B Page Page 1 of 5 of 5

400 West Cesar Chavez, Austin, TX 78701

1+(512) 416-8500

1+(512) 416-9669

www.silabs.com

Features

Four derived outputs at frequencies specified by

Hewlett Packard Computer Peripherals Bristol/Boise

(CPB)

Less than ±250 ps cycle-to-cycle jitter

(13.2 MHz clock excluded derated to ±400 ps)

Less than ±350 ps absolute jitter

Supports 3.3V operation

TTL compatible logic: VIL = 0.8V max., VIH = 2.0V min.,

VOL = 0.4V max., and VOH = 2.4V min.

OE pin has internal pull-up

45/55% duty cycle on all outputs

output drivers

Accepts 26.5625 MHz input reference

Built-in crystal oscillator circuit. Capacitive load

presented to the crystal is approximately 14 pF

Outputs designed to drive 30 pF loads

Available in 16-pin SOIC package

Functional Description

The W173 has been defined to meet the timing signal require-

ments for Hewlett Packard CPB tape drive system.

Block Diagram

Pin Configuration

XTAL

OSC

REFIN

PLL 1

50 MHz

6.6 MHz

13.2 MHz

PLL 2

10 MHz

VDD

6.6MHZ

GND

13.2MHZ

VDD

GND

10MHZ

VDD

GND

VDD

50MHZ

VDD

GND

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